A method, comprising: providing a first signal input and a second signal input to a first multiple clock domain block wherein the first signal input and the second signal input respectively have a first clock frequency and a second clock frequency first converting a first signal rate of the first signal input to a first toggle rate second converting a second signal rate of the second signal input to a second toggle rate normalizing the first toggle rate and the second toggle rate to a common multiple clock frequency of the first clock frequency and the second clock frequency propagating the first toggle rate and the second toggle rate through the first multiple clock domain block to provide a signal output estimating switching activity of the first multiple clock domain block in response to the propagating to provide the signal output to generate a first switching activity estimate estimating switching activity of a second multiple clock domain block following the first multiple clock domain block in a propagation chain to generate a second switching activity estimate determining a power consumption estimate based on the first and second switching activity estimates determining a circuit design based on the power consumption estimate and implementing the circuit design in a chip.ĩ. The method according to claim 1, wherein the first clock domain and the second clock domain are reduced to a single common multiple clock domain responsive to the converting.Ĩ. The method according to claim 5, further comprising estimating power consumption of the propagation chain based on a combination of the first and second switching activity estimates.ħ. The method according to claim 1, wherein the common multiple clock frequency is a least common multiple frequency of the first frequency and the second frequency.Ħ. The method according to claim 3, wherein the first toggle rate and the second toggle rate are respectively obtained from a first signal rate of the first signal input and a second signal rate of the second signal input as well as respectively from the first frequency and the second frequency.ĥ. The method according to claim 1, wherein the converting comprises: obtaining a first toggle rate for the first frequency of the first signal input and a second toggle rate for the second frequency of the second signal input and normalizing the first toggle rate and the second toggle rate to the common multiple clock frequency.Ĥ. The method according to claim 1, further comprising: estimating power consumption of the propagation chain based on the first and second switching activity estimates wherein the outputting is of the power consumption estimated.ģ. A method, comprising: providing a first signal input and a second signal input to a first multiple clock domain object wherein the first signal input is for a first clock domain wherein the second signal input is for a second clock domain wherein the first clock domain is associated with a first frequency wherein the second clock domain is associated with a second frequency different from the first frequency converting the first signal input and the second signal input to a common multiple clock frequency obtaining a signal output from the first multiple clock domain object responsive to the common multiple clock frequency and estimating switching activity for the first multiple clock domain object for operation based on the common multiple clock frequency to generate a first switching activity estimate estimating switching activity for a second multiple clock domain object to generate a second switching activity estimate, wherein the second multiple clock domain object follows the first multiple clock domain object in a propagation chain, and wherein one of the first and second switching activity estimates is an overestimate and the other of the first and second switching activity estimates is an underestimate outputting an output estimate associated with the first and second switching activity estimates determining a circuit design based on the output estimate and programming a chip using the circuit design.Ģ.